The present invention relates to an encoding method and a memory apparatus applicable preferably to a multi-valued recording flash memory, a memory card using that flash memory and so on.
In recent years, as the memory apparatus, semiconductor memories such as flash memories have been widely used. In the flash memory, data are recorded by using cell arrays that comprise a large number of memory cells (numbering usually about 65 million) comprising floating gates (charge storage layer) and control gates arranged in layered fashion on a semiconductor substrate (see FIG. 16). In this case, each of the cell arrays retains data as charge quantities stored in floating gates.
FIGS. 17A and 17B illustrate a structure of a memory cell 100 used in a flash memory. That is, the memory cell 100 is so formed as to stack a charge storage layer (floating gate) 102 and a control gate 103 on a semiconductor substrate 101. When a data item is to be written to the memory cell 100, the quantity of charge held in the floating gate 102 is controlled so that it is reached to one of two threshold voltages shown in FIG. 18 according to the data (xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d) to be recorded. On the other hand, when the data item is to be read from the memory cell 100, by using a reference voltage set between the two threshold voltages, it is determined that the data item in the memory cell 100 is judged to be xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d depending on whether the threshold voltage of the memory cell 100 is higher or lower than the reference voltage.
It is critical to semiconductor memories to prevent declines in reliability stemming from diverse effects of high-integration, high-density circuit implementation. As part of the effort to preserve memory device reliability, an error correcting circuit based on an error correcting code such as the Hamming code is often incorporated in the semiconductor memory in order to counter aging-induced failures such as faulty cells, resulting in particular from an increasing number of write and erase operations.
The error correcting code is a redundant code called check data attached to information data and then the check data are used to correct an error in the entire code. For example, 10-bit check data as shown in FIG. 19 are added to an abbreviated Hamming code for a 512-bit block of information data so that, even if one error occurs in the 522-bit code, the error may be corrected.
FIG. 20 shows a structure of a flash memory 110 incorporating an error correcting circuit based on the Hamming code therein. The flash memory 110 comprises cell arrays 111 having a plurality of memory cells, an encoder 112 converting input data Din into an abbreviated Hamming code to provide write data WD to be written to the cell arrays 111 and a Hamming code decoder 113 providing output data Dout by subjecting read data RD retrieved from the cell arrays 111 to an error correction process. In this case, the encoder 112 and Hamming code decoder 113 constitute an error correcting circuit. The encoder 112 adds 10-bit check data to every 512-bit block of input data Din and the abbreviated Hamming code for the 512-bit information data is created.
In the flash memory 110 shown in FIG. 20, a data write operation takes place as follows. That is, input data Din are first inputted to the encoder 112. Then, the encoder 112 converts the input data Din into the abbreviated Hamming code for 512-bit information data, thereby generating write data WD. The write data WD outputted from the encoder 112 are fed and written to the cell arrays 111.
On the other hand, a data read operation is carried out as follows. Read data RD retrieved from the cell arrays 111 are inputted to the Hamming code decoder 113. If one code of the read data RD contains no error, the Hamming code decoder 113 outputs the information data unchanged as output data Dout. If one code of the read data RD has one erroneous bit, the Hamming code decoder 113 outputs the information data as the output data Dout after correcting the error.
Next, an example in which an abbreviated BCH code (Bose-Chaudhuri-Hocquenghem code) is used as an error correcting code capable of correcting two errors in one code will be described. The BCH code and techniques of code abbreviation are discussed illustratively by Hideki Imai in xe2x80x9cCode Theoriesxe2x80x9d (Institute of Electronics, Information and Communication Engineers of Japan) among others. For example, 20-bit check data are added to the abbreviated BCH code for 512-bit information data as shown in FIG. 21, thereby enabling to correct two errors in the 532-bit code.
FIG. 22 shows a structure of a flash memory 120 incorporating an error correcting circuit based on the BCH code. The flash memory 120 comprises cell arrays 121 having a plurality of memory cells, an encoder 122 for converting input data Din into an abbreviated BCH code to provide write data WD to be written to the cell arrays 121 and a BCH code decoder 123 for subjecting read data RD retrieved from the cell arrays 121 to an error correction process to provide output data Dout. In this case, the encoder 122 and the BCH code decoder 123 constitute an error correcting circuit. The encoder 122 adds 20-bit check data to every 512-bit block of input data Din and the abbreviated BCH code capable of correcting two errors regarding the 512-bit information data is created.
In the flash memory 120 shown in FIG. 22, a data write operation takes place as follows. That is, input data Din are first inputted to the encoder 122. Then, the encoder 122 converts the input data Din into the abbreviated BCH code for 512-bit information data, thereby generating write data WD. The write data WD outputted from the encoder 122 are fed and written to the cell arrays 121.
On the other hand, a data read operation is carried out as follows. Read data RD retrieved from the cell arrays 121 is inputted to the BCH code decoder 123. If one code of the read data RD contains no error, the BCH code decoder 123 outputs the information data unchanged as output data Dout. If one code of the read data RD has one or two erroneous bits, the information data are outputted as the output data Dout after correcting the error.
As shown in FIGS. 20 and 22, the error correcting circuit incorporated in the flash memory 110 or 120 can suppress errors of written data despite a certain number of faulty cells caused by aging. However, generally in the error correcting code, a relatively large quantity of the check data, which are redundant check data, are required to correct a fairly large number of errors and thus, the number of memory cells to be used is increased as well as the scale of the error correcting circuit to be incorporated is enlarged.
Next, a memory card constituted by a plurality of flash memories (flash memory chips) will be described. As a memory device for storing quantities of data that cannot be handled by a single-chip flash memory, the memory card includes multiple flash memories and a controller.
FIG. 23 shows a structure of a memory card 130 with a controller having an error correcting circuit based on the BCH code. The memory card 130 includes two flash memories 131 and 132 and a controller 133 for writing and reading data to and from these flash memories 131 and 132.
The controller 133 comprises a card interface 134 for exchanging data with an entity outside the card, an encoder 135 for converting input data Din into an abbreviated BCH code to provide write data WD to be written to the flash memories 131 and 132, a BCH code decoder 136 for subjecting read data RD from the flash memories 131 and 132 to an error correction process to provide output data Dout, and a flash interface 137 for controlling the writing and reading of data to and from the flash memories 131 and 132.
In the above structure, the encoder 135 and the BCH code decoder 136 constitute an error correcting circuit. The encoder 135 adds 20-bit check data to every 512-bit block of input data Din, thus creating an abbreviated BCH code capable of correcting two errors regarding the 512-bit information data.
In the memory card 130 shown in FIG. 23, a data write operation takes place as follows. That is, input data Din are first taken into the card by the card interface 134 and supplied to the encoder 135. Then, the encoder 135 converts the input data Din into the abbreviated BCH code for 512-bit information data, thereby generating write data WD. The write data WD outputted from the encoder 135 are written to the flash memory 131 or 132 under control of the flash interface 137.
On the other hand, a data read operation is carried out as follows. Read data RD retrieved from the flash memory 131 or 132 under control of the flash interface 137 are inputted to the BCH code decoder 136. If one code of the read data RD contains no error, the BCH code decoder 136 outputs the information data unchanged as output data Dout. If one code of the read data RD has one or two erroneous bits, the BCH code decoder 136 outputs the information data as the output data Dout after correcting the error(s). In this way, the output data Dout are outputted from the BCH code decoder 136 to an entity outside the card via the card interface 134.
As described above, the error correcting code is also used in a memory card made of a plurality of flash memories. If a controller is used for error correction, it is possible to have a characteristic that error correcting circuit larger than an error correcting circuit incorporated in the flash memory is obtained so that the greater number of errors may be corrected.
Next, multi-value recording of a flash memory will be described. In recent years, flash memories are proposed for multi-bits recording per cell in an effort to increase storage capacity of the flash memory. For example, as shown in FIGS. 24A through 24D, the quantity of charge accumulated in a floating gate 102 in a memory cell 100 of a flash memory for four-value recording is controlled so that it may attain one of four threshold voltages shown in FIG. 25 representing a data item to be stored (xe2x80x9c11,xe2x80x9d xe2x80x9c10,xe2x80x9d xe2x80x9c01xe2x80x9d or xe2x80x9c00xe2x80x9d). When data are read, three reference voltages each established between the respective adjacent threshold values are used. By comparing the threshold value in the memory cell 100 with each of the reference voltages, the data from the memory cell 100 are retrieved. This arrangement allows each memory cell 100 to store two-bit information.
Multi-value recording flash memories may, as with their binary recording counterparts, utilize an error correcting circuit as well. FIG. 26 shows a structure of a flash memory 140 for 16-value (4-bit) recording incorporating an error correcting circuit based on the BCH code. The flash memory 140 comprises cell arrays 141 having a plurality of memory cells, an encoder 142 for converting input data Din into an abbreviated BCH code to provide write data WD to be written to the cell arrays 141 and a one-bit/four-bit converter 143 for converting write data WD outputted from the encoder 142 from serial data format to four-bit parallel data format and supplying the converted data to the cell arrays 141.
The flash memory 140 also includes a four-bit/one-bit converter 144 for converting read data RD retrieved from the cell arrays 141 from four-bit parallel data format to serial data format and a BCH code decoder 145 for providing output data Dout by subjecting to an error correction process the read data RD converted to serial data by the four-bit/one-bit converter 144. In this case, the encoder 142 and the BCH code decoder 145 constitute an error correcting circuit. The encoder 142 adds 20-bit check data to every 512-bit block of input data Din, thereby creating an abbreviated BCH code capable of correcting two errors regarding the 512-bit information data.
In the flash memory 140 shown in FIG. 26, a data write operation takes place as follows. That is, input data Din are first inputted to the encoder 142. Then, the encoder 142 converts the input data Din into the abbreviated BCH code for 512-bit information data, thereby generating write data WD. The write data WD outputted from the encoder 142 are converted by the one-bit/four-bit converter 143 from serial data format to four-bit parallel data format (four-bit data for storage into memory cells), thus supplying the write data WD to the cell arrays 141 and writing the data WD consecutively to each of memory cells making up the cell arrays 141.
On the other hand, a data read operation is carried out as follows. Read data RD retrieved from cell arrays 141 are converted by the four-bit/one-bit converter 144 from four-bit parallel data format to serial data format. The converted serial data are supplied to the BCH code decoder 145. If one code of the read data RD contains no error, the BCH code decoder 145 outputs the information data unchanged as output data Dout. If one code of the read data RD has one or two erroneous bits, the BCH code decoder 145 outputs the information data as the output data Dout after correcting the error(s).
The multi-value recording flash memories such as the flash memory 140 shown in FIG. 26 have such a characteristic that a single faulty cell causes multiple erroneous bits. Since conventional flash memories have stored one bit per memory cell, these memories principally have used code systems for bit error correction as their error correcting code. However, if a single faulty memory cell results in a plurality of erroneous bits, the error correcting code for bit-by-bit error correction is inefficient.
For example, in a flash memory wherein each memory stores four bits of data, if a single memory cell is found inaccessible, four correcting codes have to be used to correct this error. As described above, if the above error correcting code is used to correct many such errors, a large error correcting circuit is needed so that this causes a disadvantage of an expanded scale of the error correcting circuit. Because an increasing amount of redundant data needs to be added in order to correct many errors, numerous memory cells are required, which poses another disadvantage.
It is therefore an object of the present invention to provide a memory apparatus having an error correcting circuit of a small scale and a limited number of memory cells, wherein it may maintain sufficient performance by a small number of correcting errors. It is another object of the present invention to provide an encoding method and a memory apparatus using that method, whereby the length of a code is extended while data exchanges with an outside entity are still carried out, for example, in units of bytes.
In carrying out the invention and according to one aspect thereof, there is provided a memory apparatus comprising cell arrays having a plurality of memory cells each storing multi-bit information, an encoder for converting input data into a Reed-Solomon code to provide write data to be written to the cell arrays and a Reed-Solomon code decoder for subjecting read data retrieved from the cell arrays to an error correction process to provide output data.
According to another aspect of the invention, there is provided a memory apparatus comprising a memory portion having cell arrays made of a plurality of memory cells each storing multi-bit data and a controller for writing and reading data to and from the memory portion wherein the controller includes an encoder for converting input data into a Reed-Solomon code to provide write data to be written to the memory portion and a Reed-Solomon code decoder for subjecting read data retrieved from the memory portion to an error correction process to provide output data.
With the present invention, each memory cell of the cell arrays stores multi-bit data. For a write operation, the encoder converts input data into a Reed-Solomon code as write data to be written to the cell arrays. The Reed-Solomon code reckons a plurality of bits as one byte and is an error correction code used for error correction in units of bytes. For a read operation, multi-bit data are read from each memory cell of the cell arrays and the read data are subjected to an error correction process by the Reed-Solomon code decoder, thereby providing output data.
In this way, the Reed-Solomon code for error correction in units of bytes is thus used as the error correcting code for the memory apparatus made of memory cells each storing multi-bit data so that it is possible to provide sufficient performance involving a limited number of correcting errors. This makes it possible to reduce the error correcting circuit in scale with a smaller number of memory cells to be used than before.
Further, according to a further aspect of the invention, there is provided an encoding method comprising the steps of supplementing (n-m) bit data with m-bit data for conversion into n-bit data, n being greater than m, encoding the n-bit data using a Reed-Solomon code reckoning n bits as one symbol, and outputting as information data the m-bit data before supplementing the (n-m) bit data while outputting as check data the m-bit data after having undergone n-bit/m-bit conversion.
Further, according to an even further aspect of the invention, there is provided a memory apparatus comprising cell arrays having a plurality of memory cells, an encoder for converting input data into an error correcting code to provide write data to be written to the cell arrays, and a decoder for subjecting read data retrieved from the cell arrays to an error correction process to provide output data, characterized in that the encoder supplements (n-m) bit data with m-bit input data for conversion into n-bit data, n being greater than m, encodes the n-bit data using a Reed-Solomon code reckoning n bits as one symbol and outputs as information data the m-bit data before supplementing the (n-m) bit data while outputting as check data the m-bit data after having undergone n-bit/m-bit conversion and that the decoder supplements the (n-m) bit data relating to an information data part thereof with the m-bit read data retrieved from the cell arrays for conversion into n-bit data, subjects a check data part to m-bit/n-bit conversion into n-bit data, thereafter submits the converted n-bit data to an error correction process and provides as the output data an m-bit data part in the corrected n-bit information data.
Further, according to a still further aspect of the invention, there is provided a memory apparatus comprising a memory portion having cell arrays made of a plurality of memory cells and a controller for writing and reading data to and from the memory portion, characterized in that the controller includes an encoder for converting input data into an error correcting code to provide write data to be written to the memory portion, and a decoder for subjecting read data retrieved from the memory portion to an error correction process to provide output data, wherein the encoder supplements (n-n) bit data with m-bit input data for conversion into n-bit data, n being greater than m, encodes the n-bit data using a Reed-Solomon code reckoning n bits as one symbol and outputs as information data the m-bit data before supplementing the (n-m) bit data while outputting as check data the m-bit data after having undergone n-bit/m-bit conversion, and wherein the decoder supplements the n-m bit data with m-bit read data retrieved from the cell arrays for conversion into n-bit data relating to an information data part thereof, subjects a check data part of the m-bit read data to m-bit/n-bit conversion into n-bit data, thereafter submits the converted n-bit data to an error correction process and provides as the output data an m-bit data part in the corrected n-bit information data.
With the present invention, each memory cell of the cell arrays stores data of one bit or plural bits. For a write operation, m-bit input data are inputted to the encoder. The (n-m) bit data (n greater than m) of, for example, 0 are supplemented with m-bit input data for conversion into n-bit data. For example, eight-bit input data are supplemented with two-bit zeros for conversion into 10-bit data. The n-bit data are then converted to a Reed-Solomon code reckoning n bites as one symbol. The m-bit data before supplementing the (n-m) bit data are outputted as information data, while the m-bit data after having undergone n-bit/m-bit conversion are outputted as check data. Then, the m-bit data outputted from the encoder are fed and written successively to cells of the cell arrays.
The Reed-Solomon code is an error correcting code that reckons a plurality of bits as one symbol for error correction in units of symbols. For a read operation, the m-bit data retrieved from the cell arrays are inputted to the decoder. Then, the (n-m) bit data are supplemented with the m-bit data for an information data part thereof for conversion into n-bit data, and a check data part thereof is subjected to m-bit/n-bit conversion into n-bit data, whereby the Reed-Solomon code reckoning n bits as one symbol is reconstituted. Next, the reconstituted Reed-Solomon code is subjected to an error correction process. Then, an m-bit part of the corrected n-bit information data is outputted as the output data.
As described above, the input and the output data are both m-bit data whereas the encoder uses for its encoding operation the Reed-Solomon code reckoning n bits (n greater than m) as one symbol. Therefore, this makes it possible to extend the code length while maintaining data exchanges with an external entity in units of m bits. For this reason, there is no need to divide information data of a predetermined length into segments for encoding purposes. This makes it possible to reduce check data (redundant data) while preserving the continuity of decoded data.